1. Field of the Invention
The present invention relates in general to a sub-range flash-type analog-to-digital converter (hereafter called ADC), more specifically, to a flash analog-to-digital converter employing a thermal code correction scheme for correcting the mismatch between a coarse comparison and a fine comparison.
2. Description of the Related Art
Flash-type ADCs are extremely useful in high-speed applications. Fundamentally, ADCs are devices for converting analog signals to digital signals. In the conventional flash-type ADC, signal representation conversion is implemented by a direct level comparison, thereby decreasing the conversion time.
Basic flash ADCs compare the input analog signal with a set of predefined reference voltages, which are evenly spaced between a top reference voltage and a bottom reference voltage. It is evident that the basic flash ADCs need many comparators to fulfill the conversion operation. More specifically, an n-bit ADC requires 2.sup.n -1 comparators. For example, a 10-bit ADC must include 1023 comparators. Such a large number of comparators produces ADC implementation difficulties, including the need for a large amount of chip size, loading of the input analog signal, and differential and integral errors.
A sub-ranging technique is used to lessen these unwanted phenomena. In a sub-range flash ADC, the analog-to-digital conversion is implemented by two separate smaller sub-ADCs. The first sub-ADC is used to implement a coarse conversion and generates a series of most significant bits (hereafter called MSBs). The second sub-ADCs is used to implement a fine conversion in accordance with the conversion result of the coarse conversion and generates a series of least significant bits (hereafter called LSBs). Note that the total bit number of the MSBs and LSBs are equal to the bit number of the desired output digital signal of the complete ADC. For example, a 10-bit converter may be implemented by 4 MSBs and 6 LSBs, or by 5 MSBs and 5 LSBs. In addition, the total number of the required comparators may be obtained by summing the respective number of the comparators included in both of the separate sub-ADCs. For example, there are (2.sup.5 -1)+(2.sup.5 -1)=62 comparators in a 10-bit converter with 5 MSBs and 5 LSBs. Clearly, this approach help avoid the large quantity of comparators and the inherent drawbacks in the basic ADC.
In sub-range flash ADCs, the cooperation between the MSB sub-ADC and the LSB sub-ADC is a critical issue. U.S. Pat. No. 5,400,029 disclosed a sub-range flash ADC employing an intelligent cooperation scheme. FIG. 1 schematically illustrates the block diagram of the disclosed prior art sub-range flash ADC. As shown in FIG. 1, the flash ADC includes reference voltage generator 10, coarse comparing circuit 12, fine comparing circuit 14, multiplexer 16, subtraction/addition circuit 18 and logic circuit 20. Reference voltage generator 10 is used to provide a set of coarse reference voltages VRC evenly spaced between top reference voltage REF+ and bottom reference voltage REF-, and a set of fine reference voltages VRF evenly spaced within a coarse reference voltage range. Usually, reference voltage generator 10 is implemented by many resistors serially connected with each other, wherein top voltage REF+ and bottom voltage REF- are provided at both ends of these resistors. These coarse reference voltages VRC are used for coarse comparison, and, therefore, are provided to coarse comparing circuit 12. After comparing these coarse reference voltages VRC with input analog signal VI, coarse comparing circuit 12 then generates a first group of thermal codes QC representing the comparison result. The thermal codes are in a binary data format, composed of a series of data "0" followed by a series of data "1." In ADCs, each thermal code represents a comparison result of the corresponding comparator. When the corresponding reference voltage is higher than the input analog signal, the corresponding thermal code shows the data "0." When the corresponding reference voltage is below that of the input analog signal, the corresponding thermal code shows the data "1." Therefore, the intersection of the "0" series and the "1" series in the thermal codes QC indicates the coarse level of the input analog signal VI.
Multiplexer 16 and subtraction/addition circuit 18 are used to produce an intermediate analog signal VI', which is applied to fine comparing circuit 14 for fine comparison. Intermediate analog signal VI' is original input signal VI subtracted or added by a selected reference voltage VSEL, which is one of the coarse reference voltages VRC. The selected reference voltage VSEL represents a base voltage for moving input analog signal VI into a voltage range defined by the fine reference voltages VRF. Multiplexer 16 selects reference voltage VSEL from the coarse reference voltages VRC, controlled by the coarse thermal codes QC. Then subtraction/addition circuit 18 moves input analog signal VI into the voltage range defined by the fine reference voltages VRF.
The fine reference voltages VRF are evenly spaced between the voltage range by itself. Fine comparing circuit 14 compares the fine reference voltages VRF with the intermediate input signal VI', respectively, and generates the fine thermal codes QF. Finally, logic circuit 20 interprets the coarse thermal codes QC and the fine thermal codes QF and produces the output digital signal VO corresponding to the input analog signal VI.
Besides the above-indicated sub-range flash ADC, other sub-range flash ADCs may employ a slightly different approach to deal with the fine conversion. For example, in some ADCs, the multiplexer and the subtraction/addition circuit may be omitted and the original input analog signal is directly applied to the fine comparing circuit. In addition, the reference voltage generator may generate many groups of the fine reference voltages, respectively corresponding to one voltage range defined by two adjacent coarse reference voltages. One group of the fine reference voltages is selected in accordance with the coarse comparison and directly fed to the fine comparison circuit for fine conversion. However, such a sub-range flash ADC may require a lot of switching devices.
Further attention must be paid to fine comparing circuit 14 and the fine reference voltages VRF. Typically, some additional fine reference voltages (hereafter called the extension reference voltages) are provided to fine comparing circuit 14 together with the fine reference voltages VRF. These extension reference voltages usually include two portions, one being higher than the fine reference voltages and the other being lower than the fine reference voltages. In addition, fine comparing circuit 14 also includes additional comparators for comparing these extension reference voltages with the intermediate input signal VI'. These extension reference voltages are used to correct the error due to the separate coarse and fine conversion and will be discussed in the following paragraph.
FIG. 2A illustrates the prior art conversion operation of a sub-range flash ADC using the coarse conversion scheme, while FIG. 2B illustrates the fine conversion scheme.
In this simplified example, the coarse reference voltages, denoted by REF+, VRC3, VRC2, VRC1 and REF-, are used to perform a two-bit conversion and the fine reference voltages, denoted by VRC2, VRF3, VRF2, VRF1 and VRC1, are also used to perform a two-bit conversion. Therefore, this ADC is a 4-bit converter. Any input value may be located in one of the four voltage ranges defined by two adjacent coarse reference voltages. As described above, if the input value is located between the voltages REF+ and VRC3, the base voltage for moving the input value to the predefined fine comparison voltage range, denoted by VSEL in the above description, is the reference voltage VRC2. After being subtracted by the reference voltage VRC2, the input value is moved to the voltage range defined between the voltages VRC1 and VRC2. Then, in order to complete the analog-to-digital conversion, the fine comparison is performed by using VRF1, VRF2 and VRF3,. However, a conversion error in a sub-range flash ADC may happen when the input value is close to any coarse reference voltage, such as VRC1, VRC2 or VRC3.
As shown in FIG. 2A, consider an input analog signal VI to be close to the reference voltage VRC2. Assume that the true input analog signal VI is slightly higher than the coarse reference voltage VRC2. This means that the input analog signal VI is located within the voltage range between the reference voltages VRC2 and VRC3. However, if the difference voltage between the voltages VRC2 and VI is very small, for example, less than 2 mV, and the coarse comparator cannot detect such a small voltage, a conversion error happens. In such a situation, extension reference voltages, U1-U2 as seen in FIG. 2B, may be used to detect this kind of error. When the fine comparing circuit detects that the intermediate input signal VI' (same as VI in this case) is located in the voltage range between VRC2 and U1, logic circuit 20 can perform an error correction operation to modify the output digital signal. The extension reference voltages L1 and L2, also shown in FIG. 2B, are used for the same purpose. In summary, the extension reference voltages U1, U2, L1 and L2 expand the voltage range for the fine comparison and are used to ferret out any comparison error that occurs in the coarse comparing circuit.
In the conventional sub-range flash ADCs, coarse thermal codes, fine thermal codes and extension thermal codes are converted to a binary code format by using logic circuit 20 shown in FIG. 1. After conversion, logic circuit 20 also employs an error correction scheme to analyze the fine thermal codes and the extension thermal codes in order to correct the true digital output signal VO. That is, conventional ADCs correct the conversion error in the binary code format, not in the thermal code format. One example of such a correction circuit has been disclosed in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL 25, NO. 6, entitled "A 10-b 15 MHz CMOS Recycling Two-Step A/D Converter". In this article, the conversion error is corrected by latches and mathematical operation units. All thermal codes are first transformed into the binary code format, and then are corrected by the mathematical correction scheme. However, it is evident that in the conventional sub-range flash ADC, many hardware devices are needed to perform such an operation. In terms of implementation, a large amount of chip size is required to fabricate this correction circuit.